Z8 Encore!® Motor Control Flash MCUs
Product Specification
78
Table 47. PWM 0-2 H/L Duty Cycle Low Byte Register (PWMHxDL,PWMLxDL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DUTYL
00H
R/W
F31H, F33H, F35H, F37H, F39H, F3BH
ADDR
Bit
Value
(H)
Description
Position
[7]
Duty Cycle Sign
SIGN
0
1
Duty Cycle is a positive two’s complement number.
Duty Cycle is a negative two’s complement number. Output is forced to the off-
state.
[6:0], [7:0]
DUTYH and
DUTYL
PWM Duty Cycle High and Low Bytes
These two bytes, {DUTYH[7:0], DUTYL[7:0]}, form a 14-bit signed value (Bits 5
and 6 of the High Byte are always 0). The value is compared to the current 12-bit
PWM count.
PWM Control 0 Register
The PWM Control 0 (PWMCTL0) Register, shown in Table 48, controls PWM operation.
Table 48. PWM Control 0 Register (PWMCTL0)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PWMOFF OUTCTL
ALIGN
Reserved ADCTRIG Reserved READY
PWMEN
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F20H
ADDR
Pulse-Width Modulator
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
