Z8FMC16100 Series Flash MCU
Product Specification
77
Table 45. PWM Reload Low Byte Register (PWMRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PWMRL
FF
R/W
F2FH
ADDR
PWMRH and PWMRL—PWM Reload Register High and Low
These two bytes form the 12-bit Reload value, {PWMRH[3:0], PWMRL[7:0]}. This value
sets the PWM period.
PWM 0–2 Duty Cycle High and Low Byte Registers
The PWM 0–2 H/L Duty Cycle High and Low Byte (PWMxDH and PWMxDL) registers,
shown in Table 46 and Table 47, set the duty cycle of the PWM signal. This 14-bit signed
value is compared to the PWM count value to determine the PWM output. Reads from
these registers always return the values from the temporary holding registers. The PWM
duty cycle value is not used by the PWM generator until the next PWM reload event
occurs.
PWM Duty Cycle Value
PWM Duty Cycle =
PWM Reload Value
Writing a negative value (DUTYH[7] = 1) forces the PWM to be OFF for the full PWM
period. Writing a positive value greater than the 12-bit PWM reload value forces the PWM
to be ON for the full PWM period.
Table 46. PWM 0-2 H/L Duty Cycle High Byte Register (PWMHxDH,PWMLxDH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
SIGN
Reserved
00
DUTYH
0
0_0000
R/W
R/W
R/W
F30H, F32H, F34H, F36H, F38H, F3AH
ADDR
PS024604-1005
P R E L I M I N A R Y
PWM 0–2 Duty Cycle High and Low Byte
ZILOG [ ZILOG, INC. ]
