Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
24
Table 6. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
PHCTL
PHIN
Reset (Hex)
00
XX
00
Page #
38
42
FED
FEE
FEF
Port H Control
Port H Input Data
Port H Output Data
PHOUT
43
Watch-Dog Timer (WDT)
FF0
FF1
FF2
FF3
Watch-Dog Timer Control
WDTCTL
WDTU
WDTH
WDTL
—
XXX00000b
75
76
76
76
Watch-Dog Timer Reload Upper Byte
Watch-Dog Timer Reload High Byte
Watch-Dog Timer Reload Low Byte
Reserved
FF
FF
FF
XX
FF4--FF7
Flash Memory Controller
FF8
FF8
FF9
FFA
FFB
Flash Control
Flash Status
Flash Page Select
Flash Programming Frequency High Byte
Flash Programming Frequency Low Byte
FCTL
FSTAT
FPS
FFREQH
FFREQL
00
00
00
00
00
144
145
146
147
147
eZ8 CPU
FFC
FFD
FFE
FFF
Flags
—
RP
SPH
SPL
XX
XX
XX
XX
Refer to the eZ8
CPU User
Manual
Register Pointer
Stack Pointer High Byte
Stack Pointer Low Byte
XX=Undefined
PS017610-0404
Register File Address Map
ZILOG [ ZILOG, INC. ]
