Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
22
Table 6. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
SPISTAT
SPIMODE
—
SPIBRH
SPIBRL
—
Reset (Hex)
01
00
XX
FF
FF
XX
Page #
108
109
F62
SPI Status
F63
SPI Mode
F64-F65
F66
F67
Reserved
SPI Baud Rate High Byte
SPI Baud Rate Low Byte
Reserved
110
110
F68-F69
Analog-to-Digital Converter (ADC)
F70
F71
F72
F73
ADC Control
Reserved
ADC Data High Byte
ADC Data Low Bits
Reserved
ADCCTL
—
ADCD_H
ADCD_L
—
20
135
XX
XX
XX
XX
137
137
F74-FAF
DMA 0
FB0
FB1
FB2
FB3
DMA0 Control
DMA0 I/O Address
DMA0 End/Start Address High Nibble
DMA0 Start Address Low Byte
DMA0 End Address Low Byte
DMA0CTL
DMA0IO
DMA0H
DMA0START XX
DMA0END
00
XX
XX
124
125
126
127
128
FB4
XX
DMA 1
FB8
FB9
FBA
FBB
FBC
DMA1 Control
DMA1 I/O Address
DMA1 End/Start Address High Nibble
DMA1 Start Address Low Byte
DMA1 End Address Low Byte
DMA1CTL
DMA1IO
DMA1H
DMA1START XX
DMA1END XX
00
XX
XX
124
125
126
127
128
DMA ADC
FBD
FBE
DMA_ADC Address
DMA_ADC Control
DMA_ADC Status
DMAA_ADDR XX
DMAACTL 00
DMAASTAT 00
128
130
131
FBF
Interrupt Controller
FC0
FC1
FC2
FC3
FC4
FC5
FC6
FC7
Interrupt Request 0
IRQ0
00
00
00
00
00
00
00
00
00
XX
00
48
51
51
49
52
52
50
53
53
IRQ0 Enable High Bit
IRQ0 Enable Low Bit
Interrupt Request 1
IRQ1 Enable High Bit
IRQ1 Enable Low Bit
Interrupt Request 2
IRQ2 Enable High Bit
IRQ2 Enable Low Bit
Reserved
IRQ0ENH
IRQ0ENL
IRQ1
IRQ1ENH
IRQ1ENL
IRQ2
IRQ2ENH
IRQ2ENL
—
FC8
FC9-FCC
FCD
Interrupt Edge Select
IRQES
54
XX=Undefined
PS017610-0404
Register File Address Map
ZILOG [ ZILOG, INC. ]
