Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
20
Register File Address Map
Table 6 provides the address map for the Register File of the Z8F640x family of products.
Not all devices and package styles in the Z8F640x family support Timer 3 and all of the
GPIO Ports. Consider registers for unimplemented peripherals as Reserved.
Table 6. Register File Address Map
Address (Hex) Register Description
General Purpose RAM
Mnemonic
Reset (Hex)
Page #
000-EFF
General-Purpose Register File RAM
—
XX
Timer 0
F00
F01
F02
F03
F04
F05
F06
F07
Timer 0 High Byte
Timer 0 Low Byte
T0H
T0L
00
01
FF
FF
00
00
XX
00
66
66
67
67
69
69
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM High Byte
Timer 0 PWM Low Byte
Reserved
T0RH
T0RL
T0PWMH
T0PWML
—
Timer 0 Control
T0CTL
70
Timer 1
F08
F09
F0A
F0B
F0C
F0D
F0E
Timer 1 High Byte
Timer 1 Low Byte
T1H
T1L
00
01
FF
FF
00
00
XX
00
66
66
67
67
69
69
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM High Byte
Timer 1 PWM Low Byte
Reserved
T1RH
T1RL
T1PWMH
T1PWML
—
F0F
Timer 1 Control
T1CTL
70
Timer 2
F10
F11
F12
F13
F14
F15
F16
F17
Timer 2 High Byte
Timer 2 Low Byte
T2H
T2L
00
01
FF
FF
00
00
XX
00
66
66
67
67
69
69
Timer 2 Reload High Byte
Timer 2 Reload Low Byte
Timer 2 PWM High Byte
Timer 2 PWM Low Byte
Reserved
T2RH
T2RL
T2PWMH
T2PWML
—
Timer 2 Control
T2CTL
70
XX=Undefined
PS017610-0404
Register File Address Map
ZILOG [ ZILOG, INC. ]
