Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
25
Reset and Stop Mode Recovery
Overview
The Reset Controller within the Z8F640x family devices controls Reset and STOP Mode
Recovery operation. In typical operation, the following events cause a Reset to occur:
•
•
•
Power-On Reset (POR)
Voltage Brown-Out (VBO)
Watch-Dog Timer time-out (when configured via the WDT_RESOption Bit to initiate
a reset)
•
•
External RESET pin assertion
On-Chip Debugger initiated Reset (OCDCTL[1] set to 1)
When the Z8F640x family device is in Stop mode, a Stop Mode Recovery is initiated by
either of the following:
•
•
•
Watch-Dog Timer time-out
GPIO Port input pin transition on an enabled Stop Mode Recovery source
DBG pin driven Low
Reset Types
The Z8F640x family provides several different types of Reset operation. Stop Mode
Recovery is considered a form of Reset. The type of Reset is a function of both the current
operating mode of the Z8F640x family device and the source of the Reset. Table 7 lists the
types of Reset and their operating characteristics. The System Reset is longer than the
Short Reset to allow additional time for external oscillator start-up.
Table 7. Reset and Stop Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
eZ8 CPU Reset Latency (Delay)
Reset Type
System Reset
Short Reset
Control Registers
Reset (as applicable)
Reset (as applicable)
Reset
Reset
Reset
514 WDT Oscillator cycles + 16 System Clock cycles
66 WDT Oscillator cycles + 16 System Clock cycles
514 WDT Oscillator cycles + 16 System Clock cycles
Stop Mode Recovery Unaffected, except
WDT_CTL register
PS017610-0404
Reset and Stop Mode Recovery
ZILOG [ ZILOG, INC. ]
