Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
21
Table 6. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
Reset (Hex)
Page #
Timer 3 (not available in 40- and 44- Pin Packages)
F18
F19
Timer 3 High Byte
Timer 3 Low Byte
Timer 3 Reload High Byte
Timer 3 Reload Low Byte
Timer 3 PWM High Byte
Timer 3 PWM Low Byte
Reserved
T3H
T3L
00
01
FF
FF
00
00
XX
00
66
66
67
67
69
69
F1A
F1B
F1C
F1D
F1E
T3RH
T3RL
T3PWMH
T3PWML
—
F1F
F20-F3F
Timer 3 Control
Reserved
T3CTL
—
70
XX
UART 0
F40
UART0 Transmit Data
UART0 Receive Data
UART0 Status 0
UART0 Control 0
UART0 Control 1
UART0 Status 1
Reserved
UART0 Baud Rate High Byte
UART0 Baud Rate Low Byte
U0TXD
U0RXD
U0STAT0
U0CTL0
U0CTL1
U0STAT1
—
XX
XX
0000011Xb
00
00
00
XX
FF
FF
86
87
87
89
89
87
F41
F42
F43
F44
F45
F46
F47
U0BRH
U0BRL
91
91
UART 1
F48
UART1 Transmit Data
UART1 Receive Data
UART1 Status 0
UART1 Control 0
UART1 Control 1
UART1 Status 1
Reserved
UART1 Baud Rate High Byte
UART1 Baud Rate Low Byte
U1TXD
U1RXD
U1STAT0
U1CTL0
U1CTL1
U1STAT1
—
XX
XX
0000011Xb
00
00
00
XX
FF
FF
86
87
87
89
89
87
F49
F4A
F4B
F4C
F4D
F4E
F4F
U1BRH
U1BRL
91
91
2
I C
F50
F51
F52
F53
F54
2
I C Data
I2CDATA
I2CSTAT
I2CCTL
I2CBRH
I2CBRL
—
00
80
00
FF
FF
XX
118
118
119
121
121
2
I C Status
2
I C Control
2
I C Baud Rate High Byte
2
I C Baud Rate Low Byte
F55-F5F
Reserved
Serial Peripheral Interface (SPI)
F60
F61
SPI Data
SPI Control
SPIDATA
SPICTL
XX
00
106
107
XX=Undefined
PS017610-0404
Register File Address Map
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