Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
Interrupts. The MCU has six different interrupts from six
different sources. The interrupts are maskable and priori-
tized (Figure 28). The six sources are divided as follows:
four sources are claimed by Port 3 lines P33-P30) and two
in counter/timers. The Interrupt Mask Register globally or
individually enables or disables the six interrupt requests
(Table 10).
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
IRQ (D6, D7)
Select
IRQ
IMR
IPR
6
Global
Interrupt
Enable
Interrupt
Request
Priority
Logic
Vector Select
Figure 28. Interrupt Block Diagram
Table 10. Interrupt Types, Sources, and Vectors
Name
Source
Vector Location
Comments
IRQ0
IRQ1
IRQ2
/DAV0, IRQ0
IRQ1
0, 1
2, 3
4, 5
External (P32), Rising/Falling Edge Triggered
External (P33), Falling Edge Triggered
/DAV2, IRQ2, T
External (P31), Rising/Falling Edge Triggered
IN
IRQ3
IRQ4
IRQ5
IRQ3
T0
6, 7
8, 9
External (P30), Falling Edge Triggered
Internal
Internal
TI
10, 11
40
P R E L I M I N A R Y
DS97Z8X0500
ZILOG [ ZILOG, INC. ]
