Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
Z8® STANDARD CONTROL REGISTERS
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER
% FF
SPL
SPH
0
0
0
0
0
0
0
0
0
0
U
U
0
U
1
0
1
0
U
0
U
0
REGISTER POINTER
7
6
5
4
3
2
1
0
% FE
% FD
% FC
% FB
% FA
% F9
% F8
% F7
% F6
% F5
% F4
% F3
% F2
% F1
% F0
0
0
0
0
0
0
0
RP
0
0
0
0
0
0
0
Working Register
Group Pointer
Expanded Register
Group Pointer
FLAGS
IMR
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
IRQ
0
IPR
U
0
U
1
U
0
U
0
U
1
U
1
U
0
†
*
*
P01M
P3M
P2M
PRE0
T0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
0
Z8 Reg. File
%FF
%FO
PRE1
T1
Z86E30/E40 Only
U
0
TMR
Reserved
EXPANDED REG. GROUP (F)
REGISTER
RESET CONDITION
% (F) 0F
% (F) 0E
% (F) 0D
WDTMR
U
U
U
0
1
1
0
0
1
0
*
*
Z86E30/E40 Only
Reserved
%7F
U
U
U
U
U
U
SMR2
Reserved
SMR
% (F) 0C
% (F) 0B
**
0
0
1
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCON
% (F) 0A
% (F) 09
% (F) 08
% (F) 07
Reserved
% (F) 06
% (F) 05
% (F) 04
%0F
%00
% (F) 03
% (F) 02
% (F) 01
% (F) 00
1
1
1
1
1
1
1
0
EXPANDED REG. GROUP (0)
REGISTER
RESET CONDITION
Notes:
1
1
1
1
U
U
U
U
U
U
U
U
% (0) 03
% (0) 02
% (0) 01
P3
P2
P1
P0
U = Unknown
*
*
†
For Z86E40 (ROMless) reset condition: "10110110"
Will not be reset with a STOP Mode Recovery
U
U
U
U
*
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
** Will not be reset with a STOP Mode Recovery, except Bit D0.
% (0) 00
Figure 26. Expanded Register File Architecture
36
P R E L I M I N A R Y
DS97Z8X0500
ZILOG [ ZILOG, INC. ]
