Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
mode will reduce the drive of the oscillator (OSC). The de-
fault value is 1. Note: 4 MHz is the maximum external
clock frequency when running in the low EMI oscillator
mode.
except bit 7 which is a Read Only. Bit 7 is a flag bit that is
hardware set on the condition of STOP Recovery and re-
set by a power-on cycle. Bit 6 controls whether a low or
high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits 2, 3, and 4 of the
SMR register specify the STOP-Mode Recovery Source.
The SMR is located in Bank F of the Expanded Register
Group at address 0BH.
STOP-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
STOP-Mode Recovery (Figure 31). All bits are Write Only
SMR (F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide by 16
0 OFF **
1 ON
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
Stop Mode Recovery Source
000 POR and/or External Reset
001 P30
*
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0:3
111 P2 NOR 0:7
Stop Delay
0 OFF
*
1 ON
Stop Recovery Level
0 Low *
1 High
Stop Flag
0 POR
*
1 Stop Recovery
* Default setting after RESET.
** Default setting after RESET and STOP-Mode Recovery.
Figure 31. STOP-Mode Recovery Register
(Write-Only Except Bit D7, Which is Read-Only)
44
P R E L I M I N A R Y
DS97Z8X0500
ZILOG [ ZILOG, INC. ]
