Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
internal microprocessor clock divided by four, or an exter-
nal signal input through Port 3. The Timer Mode register
configures the external timer input (P31) as an external
clock, a trigger input that can be retriggerable or non-retrig-
gerable, or as a gate input for the internal clock. Port 3 line
1
P36 serves as a timer output (T
) through which T0, T1
OUT
The counters, but not the prescalers, can be read at any
time without disturbing their value or count mode. The
clock source for T1 is user-definable and can be either the
or the internal clock can be output. The counter/timers can
be cascaded by connecting the T0 output to the input of
T1.
OSC
Internal Data Bus
D1 (SMR)
Write
Write
Read
÷ 2
PRE0
T0
T0
Initial Value
Register
Initial Value
Register
Current Value
Register
D0 (SMR)
6-Bit
Down
8-bit
Down
÷ 16
÷4
Counter
Counter
IRQ4
Internal
Clock
TOUT
P36
÷2
External Clock
Clock
Logic
6-Bit
Down
8-Bit
Down
IRQ5
÷4
Counter
Counter
Internal Clock
Gated Clock
Triggered Clock
PRE1
Initial Value
Register
T1
T1
Initial Value
Register
Current Value
Register
TIN P31
Write
Write
Internal Data Bus
Read
Figure 27. Counter/Timer Block Diagram
DS97Z8X0500
P R E L I M I N A R Y
39
ZILOG [ ZILOG, INC. ]
