Z8018x Family
MPU User Manual
23
I/O Read Cycle
TW
I/O Write Cycle
T2 TW
T1
T2
T3
T1
T3
Phi
A0
–
A19
I/O address
I/O address
Write data
D0
–
D7
Read data
WAIT
IORQ
RD
WR
Figure 13. I/O Read/Write Timing Diagram
Basic Instruction Timing
An instruction may consist of a number of machine cycles including Op
Code fetch, operand fetch, and data read/write cycles. An instruction may
also include cycles for internal processes which make the bus IDLE. The
example in Figure 14 illustrates the bus timing for the data transfer
instruction LD (IX+d),g.
UM005001-ZMP0400
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