Z8018008VSC 参数 Datasheet PDF下载

Z8018x Family

MPU User Manual

Wait States (TW) are inserted as previously described for Op Code fetch

cycles. Figure 11 illustrates the read/write timing without Wait States

(Tw), while Figure 12 illustrates read/write timing with Wait States (TW).

Read Cycle

Write Cycle

Phi

–

A19

Memory address

Write data

Memory address

Read data

D0–D7

WAIT

MREQ

Figure 11. Memory Read/Write (without Wait State) Timing Diagram

UM005001-ZMP0400

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