Z8018x Family
MPU User Manual
24
CPU internal
Operation
Displacement
Read Cycle
2nd Op Code
Fetch Cycle
1st Op Code
Fetch Cycle
Next instruction
Fetch Cycle
Memory
Write Cycle
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T1 T1 T1 T2 T3 T1 T2
Phi
A0–
A19
PC+2
PC+3
PC
PC+1
(7OH 77H)
IX+d
d
–
(DDH)
g
D0–
D7
M1
MREQ
RD
WR
Machine Cycle
MC1
MC2
MC3
MC4 MC5 MC6
MC7
NOTE: d = displacement
g = register contents
Figure 14. Instruction Timing Diagram
This instruction moves the contents of a CPU register (g) to the memory
location with address computed by adding a signed 8-bit displacement (d)
to the contents of an index register (IX).
The instruction cycle begins with the two machine cycles to read the two
byte instruction Op Code as indicated by M1 Low. Next, the instruction
operand (d) is fetched.
UM005001-ZMP0400
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