Z8018x Family
MPU User Manual
17
T2
T1
TW
T3
Phi
IORQ
RD
WR
Figure 7.
I/O Read and Write Cycles with IOC = 1 Timing Diagram
When IOC is 0, the timing of the IORQ and RD signals match the timing
required by the Z80 family of peripherals. The IORQ and RD signals go
active as a result of the rising edge of T2. This timing allows the Z8X180
to satisfy the setup times required by the Z80 peripherals on those two
signals (Figure ).
T2
T1
TW
T3
Phi
IORQ
RD
WR
Figure 8.
I/O Read and Write cycles with IOC = 0 Timing Diagram
For the remainder of this document, assume that M1E is 0 and IOC is 0.
UM005001-ZMP0400
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