Z8018x Family
MPU User Manual
306
CSI/O
Direct register bit field definitions 181
Divide ratio 134
Baud rate selection 150
Block diagram 146
Control/Status register 147, 150, 159,
160, 161, 172
External clock receivetiming diagram156
External clock transmit timing diagram
DMA
Controller (DMAC) 90
CYCLE STEAL mode timing diagram
106
Edge-sense timing diagram108
Interrupt request generation114
Level-sense timing diagram 107
Mode register (DMODE) 97
Operation 104
Status register (DSTAT) 95
TEND0 output timing diagram108
Transfer request 110
154
Internal clock receivetiming diagram155
Internal clock transmit timing diagram
153
interrupt request generation151
Operation 151
Receive/Transmit timing diagram 204
Timer initialization, count down and reload
timing diagram 163
Timer output control 163
WAIT control register 100
DMAC
Block diagram 92
Register 93
Timer output timing diagram 164
Cycle timing 87
DRAM refresh intervals 89
D
Dynamic RAM refresh control 86
Data formats 131
E
DC characteristics
Absolute maximum ratings185
Z80180 186
E clock
BUS RELEASE, SLEEP and SYSTEM
STOP modes timing diagram 201
Memory and I/O R/W cycles timing dia-
gram 201
Z8L180 189
Z8S180 187
Minimum timing example of PWEL and
PWEH timing diagram 202
Timing conditions 166
DCD0 timing diagram 139
Description, general 1
Design rules, circuit board170
Timing diagram (R/W and INTACK cy-
UM005001-ZMP0400
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