Z8018x Family
MPU User Manual
305
A
B
AC characteristics197
Baud rate selection
ASCI 142
Address generation, physical64
CSI/O 150
Address map
Block diagram 6
ASCI 117
CSI/O 146
DMAC 92
MMU 56
I/O 44
I/O address translation 57
Logical examples 55
Logical memory organization 58
Logical space configuration59
Physical address transition56
PRT 157
Bus state controller 13
Addressing
Extended 182
I/O 184
C
Indexed 182
Indirect 181
Central processing unit (CPU)14
Circuit diagram, ASCI interrupt request140
Clock generator 13
Architecture 12
ASCI
Clocked serial I/O (CSI/O) 14
CPU register configurations176
Baud rate selection 142
Block diagram 117
Clock diagram 141
Control register A0 125
Control register A1 128
Control register B 131
Functions 116
CPU timing
Basic instruction 23
BUSREQ/BUSACK Bus Exchange25
HALT and Low Power modes 31
I/O data read/write 22
Interrupt request circuit diagram140
Register descriptions 117
Status register 0 120
Status register 1 123
Internal I/O registers 41
MMU register description 60
Op Code fetch timing 18
Operand and data read/write20
RESET 25
Asynchronous serial communications interface
(ASCI) 14
Wait state generator 27
UM005001-ZMP0400
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