Z8018x Family
MPU User Manual
281
Operating Modes Summary
REQUEST ACCEPTANCES IN EACH OPERATING MODE
Table 53. Request Acceptances in Each Operating Mode
Current Normal
Status Operation
(CPU mode
and IOSTOP
Mode)
Interrupt
Acknowledge
Cycle
BUS
SYSTEM
STOP
Mode
Refresh
WAIT State Cycle
RELEASE SLEEP
Request
DMA Cycle Mode
Mode
WAIT
Acceptable
Acceptable
Not
Acceptable
Acceptable Not
Not
Not
acceptable
acceptable acceptable acceptable
Refresh Request
Refresh cycle Not
acceptable
Not
acceptable
Refresh cycle
begins at the
end MC
Refresh cycle Not Not Not
begins at the acceptable acceptable acceptable
end of MC
Request of Refresh begins at the
by the on-chip end of Machine
Refresh Controller Cycle (MC)
DREQ0
DREQ1
DMA cycle
begins at the
end of MC
DMA cycle Acceptable Acceptable
begins at the Refresh cycle DMA cycle
Acceptable
Refer to
“DMA
Controller”
for details.
Acceptable Not
*After BUS acceptable acceptable
RELEASE
cycle, DMA
cycle begins
at the end of
one MC
Not
end of MC
precedes.
begins at the
DMA cycle end of MC.
begins at the
end of one
MC
BUSREQ
Bus is released Not
Not
acceptable
Bus is released Bus is
Continue
Acceptable Acceptable
Acceptable Acceptable
at the end of
acceptable
at the end of
released at the BUS
MC
MC
end of MC
RELEASE
mode
Interrupt INT0,
INT1,
Accepted after Accepted
executing the after
Not
acceptable
Not
Not
Not
acceptable
acceptable
acceptable Return from Return from
1NT2
current
instruction.
executing the
current
instruction
SLEEP
mode to
normal
operation.
SYSTEM
STOP mode
to normal
operation
UM005001-ZMP0400
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