Z8018x Family
MPU User Manual
95
DMA Status Register (DSTAT)
DSTAT is used to enable and disable DMA transfer and DMA termination
interrupts. DSTAT also determines DMA transfer status, that is, completed
or in progress.
DMA Status Register (DSTAT: 30H)
Bit
7
6
5
DWE1
W
4
DWE0
W
3
DIE1
R/W
0
2
1
?
?
?
0
DME
R
Bit/Field
R/W
DE1
R/W
0
DE0
R/W
0
DIE0
R/W
0
Reset
1
1
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
Value Description
7
DE1 R/W
Enable Channel 1 — When DE1 = 1 and DME = 1,
channel 1 DMA is enabled. When a DMA transfer
terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC.
When DE1 = 0 and the DMA interrupt is enabled (DIE1 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE1, DWE1 is written with
0 during the same register write access. Writing DE1 to 0
disables channel 1 DMA, but DMA is restartable. Writing
DE1 to 1 enables channel 1 DMA and automatically sets
DME (DMA Main Enable) to 1. DE1 is cleared to 0 during
RESET.
UM005001-ZMP0400
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