Z8018x Family
MPU User Manual
93
Internal Address/Data Bus
DMA Status
Register : DSTAT (8)
DMA Source Address
Register ch0 : SAR0 (20)
DREQ0
DREQ1
Priority &
Request
Control
DMA Destination Address
Register ch0 : DAR0 (20)
DMA Mode
Register : DMODE (8)
DMA Byte Count
Register ch0 : BCR0 (16)
DMA/WAIT Control
Register : DCNTL (8)
DMA Destination Address
Register ch1 : MAR1 (20)
DMA I/O Address
Register ch1 : IAR1 (16)
Bus & CPU
Control
DMA Control
DMA Byte Count
Register ch1 : BCR1 (16)
TEND0
TEND1
Interrupt Request
Incrementer/Decrementer (16)
Figure 45. DMAC Block Diagram
DMAC Register Description
DMA Source Address Register Channel 0 (SAR0 I/O Address = 20H
to 22H)
Specifies the physical source address for channel 0 transfers. The register
contains 20 bits and can specify up to 1024KB memory addresses or up to
64KB I/O addresses. Channel 0 source can be memory, I/O, or memory
mapped I/O.
UM005001-ZMP0400
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