Z8018x Family
MPU User Manual
99
Table 13. Channel 0 Source
SM1
SM0
Memory/I/O
Address lncrement/Decrement
0
0
1
1
0
1
0
1
Memory
Memory
Memory
I/O
+ 1
-1
fixed
fixed
Table 14 describes all DMA TRANSFER mode combinations of DM0
DM1, SM0 SM1. Because I/O to/from I/O transfers are not implemented,
12 combinations are available.
Table 14. Transfer Mode Combinations
DM1 DM0 SM1 SM0 Transfer Mode
Increment/Decrement
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Memory to Memory
Memory to Memory
Memory* to Memory
I/O to Memory
SAR0+1, DAR0+1
SAR0-1, DAR0+1
SAR0 fixed, DAR0+ 1
SAR0 fixed DAR0+1
SAR0+1, DAR0-1
Memory to Memory
Memory to Memory
Memory to Memory
I/O to Memory
SAR0-1,DAR0-1
SAR0 fixed, DAR0-1
SAR0 fixed. DAR0-1
SAR0+ 1, DAR0 fixed
SAR0-1, DAR0 fixed
Memory to Memory*
Memory to Memory*
Reserved
Reserved
UM005001-ZMP0400
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