Z8018x Family
MPU User Manual
89
Table 11. DRAM Refresh Intervals
Insertion
Time Interval
6 MHz
CYC1 CYC0 Interval
10 MHz
8 MHz
4 MHz
2.5 MHz
0
0
1
1
0
1
0
1
10 states
20 states
40 states
80 states
(1.0 ms)*
(2.0 ms)*
(4.0 ms)*
(8.0 ms)*
(1.25 ms)*
(2.5 ms)*
(5.0 ms)*
(10.0 ms)*
1.66 ms
3.3 ms
2.5 ms
5.0 ms
10.0 ms
20.0 ms
4.0 ms
8.0 ms
6.8 ms
16.0 ms
32.0 ms
13.3 ms
* Calculated interval
Refresh Control And RESET
After RESET, based on the initialized value of RCR, refresh cycles occur
with an interval of ten clock cycles and are three clock cycles in duration.
Dynamic Ram Refresh Operation Notes
1. Refresh Cycle insertion is stopped when the CPU is in the following
states:
–
–
–
–
During RESET
When the bus is released in response to BUSREQ
During SLEEP mode
During Wait States
2. Refresh cycles are suppressed when the bus is released in response to
BUSREQ. However, the refresh timer continues to operate. Thus, the
time at which the first refresh cycle occurs after the Z8X180 re-
acquires the bus depends on the refresh timer and has no timing
relationship with the bus exchange.
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
