Z8018x Family
MPU User Manual
85
Z8X180. Figure 43 illustrates the INT1, INT2 and internal interrupts
timing.
Table 10. RETI Control Signal States
MI
Machine
Cycle
States Address Data
RD WR MREQ IORQ M1E=1 M1E=0 HALT ST
1
2
3
4
5
6
7
8
T1-T3 1st
Op Code
EDH
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
TI-T3 2nd
Op Code
4DH
T1
T1
T1
Don't
Care
3-state
3-state
3-state
EDH
Don't
Care
Don't
Care
T1-T3 1st
Op Code
T1
Don't
Care
3-state
4DH
T1-T3 2nd
Op Code
9
T1-T3 SP
data
data
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
10
T1-T3 SP+1
IOC affects the IORQ/RD signals. M1E affects the assertion of M1. One state also reflects a 1 while
the other reflects a 0
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
