Z8018x Family
MPU User Manual
86
Op Code
fetch cycle
INT1, INT2, internal interrupt acknowledge cycle
PC Stacking
Last MC
Vector Table Read
T1 T2 TW*TW* T3 Ti T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi
Starting
Address
INT1,2
A0
–
A19
M1
SP-2
Vector
SP-1
Vector+1
PC
MREQ
IORQ
RD
Starting
address (L)
Starting
address (H)
WR
PCH
PCL
D0
–
D7
ST
* Two Wait States are automatically inserted.
MC: Machine Cycle
Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram
Dynamic RAM Refresh Control
The Z8X180 incorporates a dynamic RAM refresh control circuit
including 8-bit refresh address generation and programmable refresh
timing. This circuit generates asynchronous refresh cycles inserted at the
programmable interval independent of CPU program execution. For
systems which do not use dynamic RAM, the refresh function can be
disabled.
When the internal refresh controller determines that a refresh cycle should
occur, the current instruction is interrupted at the first breakpoint between
machine cycles. The refresh cycle is inserted by placing the refresh
address on A0–A7 and the RFSH output is driven Low.
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
