eZ80L92 MCU
Product Specification
72
Bit
Position
Value Description
Not valid.
[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BUS_CYCLE
1, 2, 3
Each bus mode state is 1 eZ80 clock cycle in duration.
Each bus mode state is 2 eZ80 clock cycles in duration.
Each bus mode state is 3 eZ80 clock cycles in duration.
Each bus mode state is 4 eZ80 clock cycles in duration.
Each bus mode state is 5 eZ80 clock cycles in duration.
Each bus mode state is 6 eZ80 clock cycles in duration.
Each bus mode state is 7 eZ80 clock cycles in duration.
Each bus mode state is 8 eZ80 clock cycles in duration.
Each bus mode state is 9 eZ80 clock cycles in duration.
Each bus mode state is 10 eZ80 clock cycles in duration.
Each bus mode state is 11 eZ80 clock cycles in duration.
Each bus mode state is 12 eZ80 clock cycles in duration.
Each bus mode state is 13 eZ80 clock cycles in duration.
Each bus mode state is 14 eZ80 clock cycles in duration.
Each bus mode state is 15 eZ80 clock cycles in duration.
Notes:
1. Setting the BUS_CYCLE to 1 in Intel Bus Mode causes the ALE pin to not function properly.
2. Use of the external WAIT input pin in Z80 Mode requires that BUS_CYCLE is set to a value
greater than 1.
3. These BUS_CYCLE values are not valid in eZ80 bus mode. See Table 24.
PS013015-0316
Chip Selects and Wait States
ZILOG [ ZILOG, INC. ]
