eZ80L92 MCU
Product Specification
74
Watchdog Timer Operation
Enabling and Disabling the WDT
The Watchdog Timer is disabled upon a system reset (RESET). To enable the WDT, the
application program must set the WDT_EN bit (bit 7) of the WDT_CTL register. When
enabled, the WDT cannot be disabled without a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT—218, 222, 225, and 227 system
clock cycles. The WDT time-out period is defined by the WDT_PERIOD field of the
WDT_CTL register (WDT_CTL[1:0]). The approximate time-out periods for two
different WDT clock sources is listed in Table 26.
Table 26. Watchdog Timer Approximate Time-Out Delays
Clock Source
Divider Value
Time Out Delay
8.00 s
18
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
32.768 kHz Crystal Oscillator
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
2
22
2
128 s
25
2
1024 s
27
2
4096 s
18
2
13.1 ms
209.7 ms
1.68s
22
2
25
2
27
2
6.71s
18
2
5.2 ms*
83.9 ms*
0.67 s
22
2
25
2
27
2
2.68 s
RESET Or NMI Generation
Upon a WDT time-out, the RST_FLAG in the WDT_CTL register is set to 1. In addition,
the WDT can cause a RESET or send a nonmaskable interrupt (NMI) signal to the CPU.
The default operation is for the WDT to cause a RESET. It asserts/deasserts on the rising
edge of the clock. The RST_FLAG bit can be polled by the CPU to determine the source
of the RESET event.
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the WDT
asserts an NMI for CPU processing. The RST_FLAG bit can be polled by the CPU to
PS013015-0316
Watchdog Timer
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