eZ80L92 MCU
Product Specification
68
enabled) can be active. For I/O Chip Selects, this register defines the address to which
ADDR[15:8] is compared to generate an I/O Chip Select. All Chip Select lower bound
registers reset to 00h.
Table 22. Chip Select x Lower Bound Registers (CS0_LBR = 00A8h,
CS1_LBR = 00ABh, CS2_LBR = 00AEh, CS3_LBR = 00B1h)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
CS0_LBR Reset
CS1_LBR Reset
CS2_LBR Reset
CS3_LBR Reset
CPU Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: R/W = Read/Write.
Bit
Position
Value
Description
[7:0]
00h–FFh For Memory Chip Selects (CSx_IO = 0)
CSx_LBR
This byte specifies the lower bound of the Chip Select
address range. The upper byte of the address bus,
ADDR[23:16], is compared to the values contained in these
registers for determining whether a Memory Chip Select
signal must be generated.
For I/O Chip Selects (CSx_IO = 1)
This byte specifies the Chip Select address value.
ADDR[15:8] is compared to the values contained in these
registers for determining whether an I/O Chip Select signal
must be generated.
PS013015-0316
Chip Selects and Wait States
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