eZ80L92 MCU
Product Specification
70
Chip Select x Control Registers
The Chip Select x Control register, detailed in Table 24, enables the Chip Selects, specifies
the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip
Select 0 Control register is E8h, while the reset state for the 3 other Chip Select control
registers is 00h.
Table 24. Chip Select x Control Registers (CS0_CTL = 00AAh, CS1_CTL =
00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h)
Bit
7
1
6
1
5
1
4
0
3
1
2
0
0
0
0
R
1
0
0
0
0
R
0
0
0
0
0
R
CS0_CTL Reset
CS1_CTL Reset
CS2_CTL Reset
CS3_CTL Reset
CPU Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Note: R/W = Read/Write; R = Read Only.
Bit
Position
Value Description
[7:5]
CSx_WAIT*
000
001
010
011
100
101
110
111
0
0 WAIT states are asserted when this Chip Select is active.
1 WAIT state is asserted when this Chip Select is active.
2 WAIT states are asserted when this Chip Select is active.
3 WAIT states are asserted when this Chip Select is active.
4 WAIT states are asserted when this Chip Select is active.
5 WAIT states are asserted when this Chip Select is active.
6 WAIT states are asserted when this Chip Select is active.
7 WAIT states are asserted when this Chip Select is active.
Chip Select is configured as a Memory Chip Select.
Chip Select is configured as an I/O Chip Select.
Chip Select is disabled.
4
CSx_IO
1
3
0
CSx_EN
1
Chip Select is enabled.
[2:0]
000
Reserved.
Note: *These WAIT state settings apply only to the default eZ80 bus mode. See Table 25.
PS013015-0316
Chip Selects and Wait States
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