eZ80L92 MCU
Product Specification
71
Chip Select x Bus Mode Control Registers
The Chip Select Bus Mode register, detailed in Table 25, configures the Chip Select for
eZ80, Z80, Intel®, or Motorola Bus Modes. Changing the bus mode allows the ZLP12840
to interface to peripherals based on the Z80, Intel®-, or Motorola-style asynchronous bus
interfaces. When a bus mode other than eZ80 is programmed for a particular Chip Select,
the CSx_WAIT setting in that Chip Select Control Register is ignored.
Table 25. Chip Select x Bus Mode Control Registers (CS0_BMC = 00F0h,
CS1_BMC = 00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h)
Bit
7
0
6
0
5
0
4
0
0
0
0
R
3
0
2
0
1
1
0
0
CS0_BMC Reset
CS1_BMC Reset
CS2_BMC Reset
CS3_BMC Reset
CPU Access
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: R/W = Read/Write; R = Read Only.
Bit
Position
Value Description
[7:6]
BUS_MODE
00
01
10
11
0
eZ80 bus mode.
Z80 bus mode.
®
Intel bus mode.
Motorola bus mode.
5
Separate address and data.
AD_MUX
1
Multiplexed address and data—appears on data bus
DATA[7:0].
4
0
Reserved.
PS013015-0316
Chip Selects and Wait States
ZILOG [ ZILOG, INC. ]
