eZ80L92 MCU
Product Specification
76
Bit
Position
Value Description
27
[1:0]
WDT_PERIOD
00
01
10
11
WDT time-out period is 2 clock cycles.
25
WDT time-out period is 2 clock cycles.
22
WDT time-out period is 2 clock cycles.
18
WDT time-out period is 2 clock cycles.
Note: *RST_FLAG is only cleared by a non-WDT RESET.
Watchdog Timer Reset Register
The Watchdog Timer Reset register, described in Table 28, is an 8-bit Write-Only register.
The Watchdog Timer is reset when an A5h value followed by 5Ah is written to this
register. Any amount of time can occur between the writing of the A5h value and the 5Ah
value, so long as the WDT time-out does not occur prior to completion.
Table 28. Watchdog Timer Reset Register (WDT_RR = 0094h)
Bit
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
X
Reset
CPU Access
W
W
W
W
W
W
W
W
Note: X = Undefined; W = Write only.
Bit
Position
Value Description
[7:0]
WDT_RR
A5h
The first Write value required to reset the WDT prior to a
time-out.
5Ah
The second Write value required to reset the WDT prior to a
time-out. If an A5h, 5Ah sequence is written to WDT_RR, the
WDT timer is reset to its initial count value, and counting
resumes.
PS013015-0316
Watchdog Timer
ZILOG [ ZILOG, INC. ]
