eZ80L92 MCU
Product Specification
75
determine the source of the NMI event, provided that the last RESET was not caused by
the WDT.
Watchdog Timer Registers
Watchdog Timer Control Register
The Watchdog Timer Control register, described in Table 27, is an 8-bit Read/Write regis-
ter used to enable the Watchdog Timer, set the time-out period, indicate the source of the
most recent RESET, and select the required operation upon WDT time-out.
Table 27. Watchdog Timer Control Register (WDT_CTL = 0093h)
Bit
7
0
6
0
5
0/1
R
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
R/W
R/W
R/W
R/W
R
R/W
R/W
Note: R = Read only; R/W = Read/Write.
Bit
Position
Value Description
7
0
1
WDT is disabled.
WDT_EN
WDT is enabled. When enabled, the WDT cannot be
disabled without a full RESET.
6
0
1
WDT time-out resets the CPU.
NMI_OUT
WDT time-out generates a nonmaskable interrupt (NMI) to
the CPU.
5
0
1
RESET caused by external full-chip reset or ZDI reset.
*
RST_FLAG
RESET caused by WDT time-out. This flag is set by the WDT
time-out, even if the NMI_OUT flag is set to 1. The CPU can
poll this bit to determine the source of the RESET or NMI.
[4:3]
WDT_CLK
00
01
WDT clock source is system clock.
WDT clock source is Real-Time Clock source (32 kHz
on-chip oscillator or 50/60Hz input as set by RTC_CTRL[4]) .
10
11
0
Reserved.
Reserved.
Reserved.
2
RESERVED
Note: *RST_FLAG is only cleared by a non-WDT RESET.
PS013015-0316
Watchdog Timer
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