eZ80L92 MCU
Product Specification
67
S3
S6
S0
S1
S2
S4
S5
S7
System Clock
ADDR[23:0]
DATA[7:0]
CSx
AS
DS
R/W
DTACK
MREQ
or IORQ
Figure 16. Motorola Bus Mode Write Timing Example
Switching Between Bus Modes
Each time the bus mode controller must switch from one bus mode to another, there is a
one-cycle eZ80 system clock delay. An extra clock cycle is not required for repeated
accesses in any of the bus modes; nor is it required when the ZLP12840 switches to eZ80
Bus Mode. The extra clock cycles are not shown in the timing examples. Due to the asyn-
chronous nature of these bus protocols, the extra delay does not impact peripheral commu-
nication.
Chip Select Registers
Chip Select x Lower Bound Registers
For Memory Chip Selects, the Chip Select x Lower Bound register (see Table 22) defines
the lower bound of the address range for which the corresponding Memory Chip Select (if
PS013015-0316
Chip Selects and Wait States
ZILOG [ ZILOG, INC. ]
