eZ80L92 MCU
Product Specification
54
During Write operations, Z80 Bus Mode employs 3 states (T1, T2, and T3) as described in
Table 15.
Table 15. Z80® Bus Mode Write States
STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated Chip Select signal is asserted.
STATE T2 During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one eZ80
system clock cycle prior to the end of State T2, additional WAIT states (T
until the WAIT pin is driven High.
) are asserted
WAIT
STATE T3 During State T3, no bus signals are altered.
Z80 Bus Mode Read and Write timing is illustrated in Figure 7 and Figure 8. The Z80 Bus
Mode states can be configured for 1 to 15 eZ80 system clock cycles. In these figures, each
Z80 Bus Mode state is two eZ80 system clock cycles in duration. Figure 7 and Figure 8
also illustrate the assertion of 1 WAIT state (TWAIT) by the external peripheral during each
Z80 Bus Mode cycle.
PS013015-0316
Chip Selects and Wait States
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