eZ80L92 MCU
Product Specification
39
Table 6. GPIO Mode Selection
GPIO Px_ALT2 Px_ALT1 Px_DDR Px_DR
Mode
Bits7:0
Bits7:0
Bits7:0 Bits7:0 Port Mode
Output
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
0
Output
1
2
3
4
Input from pin
Input from pin
Open-Drain output
Open-Drain I/O
Open source I/O
Open source output
Reserved
High impedance
High impedance
0
High impedance
High impedance
1
5
6
7
High impedance
Interrupt—dual edge triggered
High impedance
Port B, C, or D—alternate function controls port I/O.
Port B, C, or D—alternate function controls port I/O.
8
9
Interrupt—active Low
Interrupt—active High
High impedance
High impedance
Interrupt—falling edge triggered High impedance
Interrupt—rising edge triggered High impedance
GPIO Mode 1. This port pin is configured as a standard digital output pin. The value
written to the Port x Data register (Px_DR) is located on the pin.
GPIO Mode 2. The port pin is configured as a standard digital input pin. The output is
tristated (high impedance). The value stored in the Port x Data register produces no effect.
As in all modes, a Read from the Port x Data register returns the pin’s value. GPIO Mode
2 is the default operating mode following a RESET.
GPIO Mode 3. The port pin is configured as open-drain I/O. The GPIO pins do not feature
an internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN
mode, an external pull-up resistor must connect the pin to the supply voltage. Writing a 0
to the Port x Data register outputs a Low at the pin. Writing a 1 to the Port x Data register
results in high-impedance output.
GPIO Mode 4. The port pin is configured as open-source I/O. The GPIO pins do not
feature an internal pull-down to the supply ground. To employ the GPIO pin in OPEN-
SOURCE mode, an external pull-down resistor must connect the pin to the supply ground.
PS013015-0316
General-Purpose Input/Output
ZILOG [ ZILOG, INC. ]
