eZ80L92 MCU
Product Specification
28
Table 3. Register Map (Continued)
Address
Reset
(hex)
CPU
Access
Page
No
(hex)
Mnemonic
Name
Universal Asynchronous Receiver/Transmitter 0 (UART0) Block
00C0
UART0_RBR
UART0_THR
UART 0 Receive Buffer Register
UART 0 Transmit Holding Register
XX
XX
02
R
W
112
111
110
UART0_BRG_L UART 0 Baud Rate Generator
Register—Low Byte
R/W
00C1
UART0_IER
UART 0 Interrupt Enable Register
00
00
R/W
R/W
112
110
UART0_BRG_H UART 0 Baud Rate Generator
Register—High Byte
00C2
00C3
UART0_IIR
UART 0 Interrupt Identification Register
UART 0 FIFO Control Register
UART 0 Line Control Register
01
00
00
R
W
113
114
115
UART0_FCTL
UART0_LCTL
R/W
Universal Asynchronous Receiver/Transmitter 0 (UART0) Block
00C4
00C5
00C6
00C7
UART0_MCTL
UART0_LSR
UART0_MSR
UART0_SPR
UART 0 Modem Control Register
UART 0 Line Status Register
UART 0 Modem Status Register
UART 0 Scratch Pad Register
00
60
XX
00
R/W
R
117
118
120
122
R
R/W
2
I C Block
2
00C8
00C9
00CA
00CB
00CC
I2C_SAR
I2C_XSAR
I2C_DR
I C Slave Address Register
00
00
00
00
F8
00
XX
R/W
R/W
R/W
R/W
R
152
152
153
154
155
157
159
2
I C Extended Slave Address Register
2
I C Data Register
2
I2C_CTL
I2C_SR
I C Control Register
2
I C Status Register
2
I2C_CCR
I2C_SRR
I C Clock Control Register
W
2
00CD
I C Software Reset Register
W
PS013015-0316
Register Map
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