eZ80L92 MCU
Product Specification
25
Register Map
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations
employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all
I/O operations (ADDR[23:16] = UU). All I/O operations using 16-bit addresses within the
range 0080h–00FFh are routed to the on-chip peripherals. External I/O Chip Selects are
not generated if the address space programmed for the I/O Chip Selects overlaps the
0080h–00FFh address range.
Registers at unused addresses within the 0080h–00FFh range assigned to on-chip
peripherals are not implemented. Read access to such addresses returns unpredictable
values and Write access produces no effect. Table 3 lists the register map for the
ZLP12840 MCU.
Table 3. Register Map
Address
(hex)
Reset
(hex)
CPU
Access
Page
No
Mnemonic
Name
Programmable Reload Counter/Timers
0080
0081
TMR0_CTL
Timer 0 Control Register
00
00
00
00
00
00
00
00
00
00
00
R/W
R
82
84
85
84
86
82
84
85
84
86
82
TMR0_DR_L
TMR0_RR_L
TMR0_DR_H
TMR0_RR_H
TMR1_CTL
Timer 0 Data Register—Low Byte
Timer 0 Reload Register—Low Byte
Timer 0 Data Register—High Byte
Timer 0 Reload Register—High Byte
Timer 1 Control Register
W
0082
R
W
0083
0084
R/W
R
TMR1_DR_L
TMR1_RR_L
TMR1_DR_H
TMR1_RR_H
TMR2_CTL
Timer 1 Data Register—Low Byte
Timer 1 Reload Register—Low Byte
Timer 1 Data Register—High Byte
Timer 1 Reload Register—High Byte
Timer 2 Control Register
W
0085
0086
R
W
R/W
Programmable Reload Counter/Timers
0087
TMR2_DR_L
TMR2_RR_L
TMR2_DR_H
TMR2_RR_H
Timer 2 Data Register—Low Byte
Timer 2 Reload Register—Low Byte
Timer 2 Data Register—High Byte
Timer 2 Reload Register—High Byte
00
00
00
00
R
W
R
84
85
84
86
0088
W
PS013015-0316
Register Map
ZILOG [ ZILOG, INC. ]
