eZ80L92 MCU
Product Specification
27
Table 3. Register Map (Continued)
Address
Reset
(hex)
CPU
Access
Page
No
(hex)
00A3
00A4
00A5
Mnemonic
PD_DDR
PD_ALT1
PD_ALT2
Name
Port D Data Direction Register
Port D Alternate Register 1
Port D Alternate Register 2
FF
00
00
R/W
R/W
R/W
43
43
43
Chip Select/Wait State Generator
00A8
00A9
00AA
00AB
00AC
00AD
00AE
00AF
00B0
00B1
CS0_LBR
CS0_UBR
CS0_CTL
CS1_LBR
CS1_UBR
CS1_CTL
CS2_LBR
CS2_UBR
CS2_CTL
CS3_LBR
Chip Select 0 Lower Bound Register
Chip Select 0 Upper Bound Register
Chip Select 0 Control Register
00
FF
E8
00
00
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
68
69
70
68
69
70
68
69
70
68
Chip Select 1 Lower Bound Register
Chip Select 1 Upper Bound Register
Chip Select 1 Control Register
Chip Select 2 Lower Bound Register
Chip Select 2 Upper Bound Register
Chip Select 2 Control Register
Chip Select 3 Lower Bound Register
Chip Select/Wait State Generator
00B2
00B3
CS3_UBR
CS3_CTL
Chip Select 3 Upper Bound Register
Chip Select 3 Control Register
00
00
R/W
R/W
69
70
Serial Peripheral Interface (SPI) Block
00B8
SPI_BRG_L
SPI Baud Rate Generator
Register—Low Byte
02
00
R/W
R/W
134
135
00B9
SPI_BRG_H
SPI Baud Rate Generator
Register—High Byte
00BA
00BB
00BC
SPI_CTL
SPI_SR
SPI Control Register
04
00
R/W
R
135
136
137
137
SPI Status Register
SPI_TSR
SPI_RBR
SPI Transmit Shift Register
SPI Receive Buffer Register
XX
XX
W
R
Infrared Encoder/Decoder Block
00BF IR_CTL Infrared Encoder/Decoder Control
00
R/W
126
PS013015-0316
Register Map
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