eZ80L92 MCU
Product Specification
26
Table 3. Register Map (Continued)
Address
Reset
(hex)
CPU
Access
Page
No
(hex)
0089
008A
Mnemonic
Name
TMR3_CTL
TMR3_DR_L
TMR3_RR_L
TMR3_DR_H
TMR3_RR_H
TMR4_CTL
TMR4_DR_L
TMR4_RR_L
TMR4_DR_H
TMR4_RR_H
TMR5_CTL
TMR5_DR_L
TMR5_RR_L
TMR5_DR_H
TMR5_RR_H
TMR_ISS
Timer 3 Control Register
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
R/W
R
82
84
85
84
86
82
84
85
84
86
82
84
85
84
86
87
Timer 3 Data Register—Low Byte
Timer 3 Reload Register—Low Byte
Timer 3 Data Register—High Byte
Timer 3 Reload Register—High Byte
Timer 4 Control Register
W
008B
R
W
008C
008D
R/W
R
Timer 4 Data Register—Low Byte
Timer 4 Reload Register—Low Byte
Timer 4 Data Register—High Byte
Timer 4 Reload Register—High Byte
Timer 5 Control Register
W
008E
R
W
008F
0090
R/W
R
Timer 5 Data Register—Low Byte
Timer 5 Reload Register—Low Byte
Timer 5 Data Register—High Byte
Timer 5 Reload Register—High Byte
Timer Input Source Select Register
W
0091
0092
R
W
R/W
Watchdog Timer
1
0093
0094
WDT_CTL
WDT_RR
Watch-Dog Timer Control Register
00/20
XX
R/W
W
75
76
Watch-Dog Timer Reset Register
General-Purpose Input/Output Ports
2
009A
009B
009C
009D
009E
009F
00A0
00A1
00A2
PB_DR
Port B Data Register
XX
FF
00
00
XX
FF
00
00
XX
R/W
R/W
R/W
R/W
42
43
43
43
42
43
43
43
42
PB_DDR
PB_ALT1
PB_ALT2
PC_DR
Port B Data Direction Register
Port B Alternate Register 1
Port B Alternate Register 2
Port C Data Register
2
R/W
PC_DDR
PC_ALT1
PC_ALT2
PD_DR
Port C Data Direction Register
Port C Alternate Register 1
Port C Alternate Register 2
Port D Data Register
R/W
R/W
R/W
2
R/W
PS013015-0316
Register Map
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