eZ80L92 MCU
Product Specification
172
Bit
Position
Value Description
1
0
The Ignore the Low Byte function of the ZDI Address Match
1 registers is disabled. If BRK_ADDR0 is set to 1, ZDI
initiates a BREAK when the entire 24-bit address,
ADDR[23:0], matches the 3-byte value {ZDI_ADDR0_U,
ZDI_ADDR0_H, ZDI_ADDR0_L}.
ign_low_0
1
The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If the BRK_ADDR1 is set to 0, ZDI
initiates a BREAK when only the upper 2 bytes of the 24-bit
address, ADDR[23:8], match the 2 bytes value
{ZDI_ADDR0_U, ZDI_ADDR0_H}. As a result, a BREAK
can occur anywhere within a 256-byte page.
0
0
1
ZDI SINGLE STEP mode is disabled.
single_step
ZDI SINGLE STEP mode is enabled. ZDI asserts a BREAK
following execution of each instruction.
ZDI Master Control Register
The ZDI Master Control register provides control of the ZLP12840. It is capable of forc-
ing a RESET and waking up the ZLP12840 from the low-power modes (HALT or
SLEEP). See Table 94.
Table 94. ZDI Master Control Register (ZDI_MASTER_CTL = 11h in ZDI
Register Write Address Spaces)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: W = Write-only.
W
W
W
W
W
W
W
W
Bit
Position
Value Description
7
0
No action.
Initiate a RESET of the ZLP12840. This bit is
automatically cleared at the end of the RESET event.
0000000 Reserved.
ZDI_RESET
1
[6:0]
PS013015-0316
Zilog Debug Interface
ZILOG [ ZILOG, INC. ]
