eZ80L92 MCU
Product Specification
171
Bit
Position
Value Description
7
0
The ZDI BREAK on the next CPU instruction is disabled.
Clearing this bit releases the CPU from its current BREAK
condition.
BRK_NEXT
1
The ZDI BREAK on the next CPU instruction is enabled.
The CPU can use multibyte Op Codes and multibyte
operands. break points only occur on the first Op Code in a
multibyte Op Code instruction. If the ZCL pin is High and
the ZDA pin is Low at the end of RESET, this bit is set to 1
and a BREAK occurs on the first instruction following the
RESET. This bit is set automatically during ZDI BREAK on
address match. A BREAK can also be forced by writing a 1
to this bit.
6
0
1
0
1
0
1
0
1
0
The ZDI BREAK, upon matching break address 3,
is disabled.
brk_addr3
The ZDI BREAK, upon matching break address 3,
is enabled.
5
The ZDI BREAK, upon matching break address 2,
is disabled.
brk_addr2
The ZDI BREAK, upon matching break address 2,
is enabled.
4
The ZDI BREAK, upon matching break address 1,
is disabled.
brk_addr1
The ZDI BREAK, upon matching break address 1,
is enabled.
3
The ZDI BREAK, upon matching break address 0,
is disabled.
brk_addr0
The ZDI BREAK, upon matching break address 0,
is enabled.
2
The Ignore the Low Byte function of the ZDI Address Match
1 registers is disabled. If BRK_ADDR1 is set to 1, ZDI
initiates a BREAK when the entire 24-bit address,
ADDR[23:0], matches the 3-byte value {ZDI_ADDR1_U,
ZDI_ADDR1_H, ZDI_ADDR1_L}.
ign_low_1
1
The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If BRK_ADDR1 is set to 1, ZDI
initiates a BREAK when only the upper 2 bytes of the 24-bit
address, ADDR[23:8], match the 2-byte value
{ZDI_ADDR1_U, ZDI_ADDR1_H}. As a result, a BREAK
can occur anywhere within a 256-byte page.
PS013015-0316
Zilog Debug Interface
ZILOG [ ZILOG, INC. ]
