eZ80L92 MCU
Product Specification
157
Table 86. I2C Status Codes (Continued)
Code
Status
B0h
Arbitration lost in address as master, slave address and Read bit received,
ACK transmitted
B8h
C0h
C8h
D0h
D8h
F8h
Data byte transmitted in SLAVE mode, ACK received
Data byte transmitted in SLAVE mode, ACK not received
Last byte transmitted in SLAVE mode, ACK received
Second Address byte and Write bit transmitted, ACK received
Second Address byte and Write bit transmitted, ACK not received
No relevant status information, IFLG = 0
If an illegal condition occurs on the I2C bus, the bus error state is entered (status code
00h). To recover from this state, the STP bit in the I2C_CTL register must be set and the
IFLG bit cleared. The I2C then returns to the idle state. No STOP condition is transmitted
on the I2C bus.
The STP and STA bits may be set to 1 at the same time to recover from the bus error. The
I2C then sends a START.
Note:
I2C Clock Control Register
The I2C_CCR register is a Write-Only register. The seven LSBs control the frequency at
which the I2C bus is sampled and the frequency of the I2C clock line (SCL) when the I2C
is in MASTER mode. The Write-Only I2C_CCR registers share the same I/O addresses as
the Read-Only I2C_SR registers. See Table 87.
Table 87. I2C Clock Control Registers (I2C_CCR = 00CCh)
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
CPU Access
Note: W = Read only.
W
W
W
W
W
W
W
W
Bit
Position
Value
Description
7
0
Reserved.
PS013015-0316
I2C Serial I/O Interface
ZILOG [ ZILOG, INC. ]
