ZL50022
Data Sheet
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode - Write Access
Characteristics
CS de-asserted time
DS de-asserted time
CS setup to DS falling
R/W setup to DS falling
Address setup to DS falling
Data setup to DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Sym.
Min.
Typ.
Max.
Units
Test Conditions2
1
2
3
4
5
6
7
8
9
tCSD
tDSD
tCSS
tRWS
tAS
15
15
0
10
5
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDS
CL = 50 pF
tCSH
tRWH
tAH
10 Data hold from DS rising
tDH
5
CL = 50 pF, RL = 1 K
(Note 1)
11 Acknowledgement delay time.
From DS low to DTA low:
Registers
tAKD
Memory
55
150
ns
ns
CL = 50 pF
CL = 50 pF
12 Acknowledgement hold time.
From DS high to DTA high
13 DTA drive high to HiZ
tAKH
tAKZ
4
12
ns
CL = 50 pF, RL = 1 K
(Note 1)
8
ns
Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to
discharge CL.
Note 2: A delay of 500 µs to 2 ms (see Section 17.2 on page 47) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
tCSS
tCSH
CS
VCT
tDSD
VCT
VCT
DS
tRWH
tRWS
R/W
tAH
tAS
VCT
VALID ADDRESS
A0-A13
D0-D15
tDS
tDH
VCT
VALID WRITE DATA
tAKZ
VCT
DTA
tAKH
tAKD
Figure 27 - Motorola Non-Multiplexed Bus Timing - Write Access
95
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