欢迎访问ic37.com |
会员登录 免费注册
发布采购

ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
 浏览型号ZL50022QCG1的Datasheet PDF文件第88页浏览型号ZL50022QCG1的Datasheet PDF文件第89页浏览型号ZL50022QCG1的Datasheet PDF文件第90页浏览型号ZL50022QCG1的Datasheet PDF文件第91页浏览型号ZL50022QCG1的Datasheet PDF文件第93页浏览型号ZL50022QCG1的Datasheet PDF文件第94页浏览型号ZL50022QCG1的Datasheet PDF文件第95页浏览型号ZL50022QCG1的Datasheet PDF文件第96页  
ZL50022  
Data Sheet  
26.0 DC Parameters  
Absolute Maximum Ratings*  
Parameter  
Symbol  
Min.  
Max.  
Units  
1
2
3
4
5
6
7
I/O Supply Voltage  
Core Supply Voltage  
Input Voltage  
Input Voltage (5 V-tolerant inputs)  
Continuous Current at Digital Outputs  
Package Power Dissipation  
Storage Temperature  
VDD_IO  
VDD_CORE  
VI_3V  
VI_5V  
Io  
-0.5  
-0.5  
-0.5  
-0.5  
5.0  
2.5  
VDD + 0.5  
7.0  
V
V
V
V
mA  
W
°C  
15  
1.5  
+125  
PD  
TS  
- 55  
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.  
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.  
Characteristics  
Operating Temperature  
Positive Supply  
Positive Supply  
Input Voltage  
Sym.  
Min.  
Typ.‡  
Max.  
Units  
1
2
3
4
5
TOP  
VDD_IO  
VDD_CORE  
VI  
-40  
3.0  
1.71  
0
25  
3.3  
1.8  
3.3  
5.0  
+85  
3.6  
1.89  
VDD_IO  
5.5  
°C  
V
V
V
V
Input Voltage on 5 V-Tolerant Inputs  
VI_5V  
0
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.  
DC Electrical Characteristics- Voltages are with respect to ground (V ) unless otherwise stated.  
ss  
Characteristics  
Sym.  
Min.  
Typ.‡  
Max.  
Units  
Test Conditions  
1
2
3
4
5
Supply Current - VDD_CORE  
Supply Current - VDD_IO  
Input High Voltage  
IDD_CORE  
IDD_IO  
VIH  
175  
75  
mA  
mA CL = 30 pF  
V
V
µA  
µA  
2.0  
Input Low Voltage  
VIL  
0.8  
5
5
Input Leakage (input pins)  
IIL  
0<VINVDD_IO  
Input Leakage (bi-directional pins)  
IBL  
See Note 1  
6
7
8
9
Weak Pullup Current  
Weak Pulldown Current  
Input Pin Capacitance  
Output High Voltage  
IPU  
IPD  
CI  
VOH  
VOL  
IOZ  
CO  
-33  
33  
3
µA  
µA  
pF  
V
V
µA  
pF  
Input at 0V  
Input at VDD_IO  
2.4  
IOH = 8 mA  
IOL = 8 mA  
0 < V < VDD  
10 Output Low Voltage  
11 Output High Impedance Leakage  
12 Output Pin Capacitance  
† Characteristics are over recommended operating conditions unless otherwise stated.  
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.  
0.4  
5
10  
5
* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).  
92  
Zarlink Semiconductor Inc.  
 复制成功!