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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
AC Electrical Characteristics- Intel Non-Multiplexed Bus Mode - Write Access  
Characteristics  
CS de-asserted time  
Sym.  
Min.  
Typ.  
Max.  
Units  
Test Conditions2  
1
2
3
4
5
6
7
8
9
tCSD  
tWS  
tRS  
tAS  
15  
10  
10  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WR setup to CS falling  
RD setup to CS falling  
Address setup to CS falling  
Data setup to CS falling  
WR hold after CS rising  
RD hold after CS rising  
Address hold after CS rising  
Data hold after CS rising  
tDS  
tWH  
tRH  
tAH  
tDH  
0
0
0
10  
5
CL = 50 pF  
CL = 50 pF, RL = 1 K  
(Note 1)  
10 Acknowledgement delay time.  
From CS low to RDY high:  
Registers  
tAKD  
Memory  
55  
150  
ns  
ns  
CL = 50 pF  
CL = 50 pF  
11 Acknowledgement hold time.  
From CS high to RDY low  
12 RDY drive low to HiZ  
tAKH  
tAKZ  
4
12  
ns  
CL = 50 pF, RL = 1 K  
(Note 1)  
8
ns  
Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to  
discharge CL.  
Note 2: A delay of 500 µs to 2 ms (Section 17.2 on page 47) must be applied before the first microprocessor access is performed  
after the RESET pin is set high.  
† Characteristics are over recommended operating conditions unless otherwise stated.  
tCSD  
VCT  
CS  
tWH  
tWS  
VCT  
WR  
tRH  
tRS  
VCT  
RD  
tAH  
tAS  
VCT  
VALID ADDRESS  
A0-A13  
D0-D15  
tDH  
tDS  
VCT  
VALID WRITE DATA  
tAKZ  
VCT  
RDY  
tAKD  
tAKH  
Figure 29 - Intel Non-Multiplexed Bus Timing - Write Access  
97  
Zarlink Semiconductor Inc.  
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