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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
Load Capacitance  
20 pF - 32 pF  
Maximum Series Resistance  
Approximate Drive Level  
35 Ω  
1 mW  
25.1.2 External Clock Oscillator  
When an external clock oscillator is used, numerous parameters must be considered. They include absolute  
frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.  
The output clock should be connected directly (not AC coupled) to the OSCi input of the device, and the OSCo  
output should be left open as shown in Figure 24 on page 91. XC is a buffered version of the 20 MHz input clock  
connected to the internal circuitry.  
+3.3 V  
OSCi  
4K DX  
+3.3 V  
20 MHz OUT  
GND  
0.1 uF  
OSCo  
XC  
No Connection  
Figure 24 - Clock Oscillator Circuit  
For applications requiring ±32 ppm clock accuracy, the following requirements should be met:  
Frequency  
20.000 MHz  
±32 ppm  
Tolerance  
Rise and Fall Time  
Duty Cycle  
10 ns  
40% to 60%  
91  
Zarlink Semiconductor Inc.  
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