ZL50022
Data Sheet
AC Electrical Characteristics† - Intel Non-Multiplexed Bus Mode - Read Access
Characteristics
CS de-asserted time
Sym.
Min.
Typ.
Max.
Units
Test Conditions2
1
2
3
4
5
6
7
8
9
tCSD
tRS
tWS
tAS
15
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD setup to CS falling
WR setup to CS falling
Address setup to CS falling
RD hold after CS rising
WR hold after CS rising
Address hold after CS rising
Data setup to RDY high
Data hold after CS rising
tRH
tWH
tAH
tDS
tDH
0
0
0
8
CL = 50 pF
CL = 50 pF, RL = 1 K
(Note 1)
7
10 Acknowledgement delay time.
From CS low to RDY high:
Registers
tAKD
Memory
75
185
ns
ns
CL = 50 pF
CL = 50 pF
11 Acknowledgement hold time.
From CS high to RDY low
12 RDY drive low to HiZ
tAKH
tAKZ
4
12
ns
CL = 50 pF, RL = 1 K
(Note 1)
8
ns
Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to
discharge CL.
Note 2: A delay of 500 µs to 2 ms (see Section 17.2 on page 47) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
† Characteristics are over recommended operating conditions unless otherwise stated.
tCSD
VCT
CS
RD
tRH
tRS
VCT
tWH
tWS
VCT
WR
tAH
tAS
VCT
VALID ADDRESS
A0-A13
D0-D15
tDH
VALID READ DATA
VCT
tDS
tAKZ
VCT
RDY
tAKD
tAKH
Figure 28 - Intel Non-Multiplexed Bus Timing - Read Access
96
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
