ZL50022
Data Sheet
External Read/Write Address: 0340H - 035FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
ST[n]
ST[n]
SBER
CBER
Bit
Name
Description
15 - 2
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
1
0
ST[n]
Stream[n] Bit Error Rate Counter Clear
When this bit is high, it resets the internal bit error counter and the stream BER
Receiver Error Register to zero.
CBER
ST[n]
Stream[n] Bit Error Rate Test Start
When this bit is high, it enables the BER receiver; starts the bit error rate test. The bit
error test result is kept in the BER Receiver Error (BRER[n]) register. Upon the
completion of the BER test, set this bit to zero. Note that the RBEREB bit must be set
in the IMS Register first.
SBER
Note: [n] denotes input stream from 0 - 31.
Table 50 - BER Receiver Control Register [n] (BRCR[n]) Bits
External Read Address: 0360H - 037FH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ST[n]
BC15
ST[n]
BC14
ST[n]
BC13
ST[n]
BC12
ST[n]
BC11
ST[n]
BC10
ST[n]
BC9
ST[n]
BC8
ST[n]
BC7
ST[n]
BC6
ST[n]
BC5
ST[n]
BC4
ST[n]
BC3
ST[n]
BC2
ST[n]
BC1
ST[n]
BC0
Bit
Name
Description
15 - 0
ST[n]
Stream[n] BER Count Bits (Read Only)
BC15 - 0
The binary value of these bits refers to the bit error counts. When it reaches its maxi-
mum value of 0xFFFF, the value will be held and will not rollover.
Note: [n] denotes input stream from 0 - 31.
Table 51 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only
85
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
