ZL50022
Data Sheet
External Read/Write Address: 0120H - 013FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
STIN[n]
Q3C2
STIN[n]
Q3C1
STIN[n]
Q3C0
STIN[n]
Q2C2
STIN[n]
Q2C1
STIN[n]
Q2C0
STIN[n]
Q1C2
STIN[n]
Q1C1
STIN[n]
Q1C0
STIN[n]
Q0C2
STIN[n]
Q0C1
STIN[n]
Q0C0
Bit
Name
Description
15 - 12
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
11 - 9
STIN[n]Q3C2 - 0 Quadrant Frame 3 Control Bits
These three bits are used to control STi[n]’s quadrant frame 3, which is defined
as Ch24 to 31, Ch48 to 63, Ch96 to 127 and Ch192 to 255 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q3C
Operation
2-0
0xx
100
101
110
111
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
8 - 6
STIN[n]Q2C2 - 0 Quadrant Frame 2 Control Bits
These three bits are used to control STi[n]’s quadrant frame 2, which is defined
as Ch16 to 23, Ch32 to 47, Ch64 to 95 and Ch128 to 191 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q2C
Operation
2-0
0xx
100
101
110
111
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
Table 46 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits
81
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
