ZL50022
Data Sheet
External Read/Write Address: 0120H - 013FH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
STIN[n]
Q3C2
STIN[n]
Q3C1
STIN[n]
Q3C0
STIN[n]
Q2C2
STIN[n]
Q2C1
STIN[n]
Q2C0
STIN[n]
Q1C2
STIN[n]
Q1C1
STIN[n]
Q1C0
STIN[n]
Q0C2
STIN[n]
Q0C1
STIN[n]
Q0C0
Bit
5 - 3
Name
Description
STIN[n]Q1C2 - 0 Quadrant Frame 1 Control Bits
These three bits are used to control STi[n]’s quadrant frame 1, which is defined
as Ch8 to 15, Ch16 to 31, Ch32 to 63 and Ch64 to 127 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q1C
Operation
2-0
0xx
100
101
110
111
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
2 - 0
STIN[n]Q0C2 - 0 Quadrant Frame 0 Control Bits
These three bits are used to control STi[n]’s quadrant frame 0, which is defined
as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q0C2-0
Operation
0xx
100
101
110
111
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
Note: [n] denotes input stream from 0 - 31.
Table 46 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits (continued)
82
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
