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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
24.2 Connection Memory Low (CM_L) Bit Assignment  
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal  
channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in  
Table 53 on page 87.  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
UA  
EN  
V/C  
SSA  
4
SSA  
3
SSA  
2
SSA  
1
SSA  
0
SCA  
7
SCA  
6
SCA  
5
SCA  
4
SCA  
3
SCA  
2
SCA  
1
SCA  
0
CMM  
=0  
Bit  
Name  
Description  
15  
UAEN  
Conversion between µ-law and A-law Enable  
When this bit is low, normal switch without µ-law/A-law conversion. Connec-  
tion memory high will be ignored.  
When this bit is high, switch with µ-law/A-law conversion, and connection  
memory high controls the conversion method.  
14  
V/C  
Variable/Constant Delay Control  
When this bit is low, the output data for this channel will be taken from con-  
stant delay memory.  
When this bit is set to high, the output data for this channel will be taken from  
variable delay memory. Note that VAREN must be set in Control Register  
first.  
13 - 9  
8 - 1  
0
SSA4 - 0 Source Stream Address  
The binary value of these 5 bits represents the input stream number.  
SCA7 - 0 Source Channel Address  
The binary value of these 8 bits represents the input channel number.  
CMM = 0 Connection Memory Mode = 0  
If this is low, the connection memory is in the normal switching mode. Bit 13 -  
1 are the source stream number and channel number.  
Note: For proper µ-law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.  
Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0  
87  
Zarlink Semiconductor Inc.  
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